The testing of memory devices in the prior art generally involves receiving inputs from several memory addresses at one time into a test vector decoding circuit and performing logic functions on those inputs. The resulting output test vectors are used to perform operations on various devices, such as compressing address circuits or disabling regulators. Once testing has been completed, the values of the output test vectors will remain consistent for the purpose of driving circuits during non-test operations of the memory device.
One possible method of triggering the test mode as disclosed in the prior art is to use two signals. For example, a WCBR signal (Write enable signal at low with the CAS signal transmitted Before the RAS signal) sent during the transmission of a supervoltage signal is often used. The supervoltage signal will have a higher potential than the standard supply voltage. This supervoltage signal may generally be applied consistently throughout both test and non-test modes of the memory device. Only during the test mode, however, will the WCBR signal deliberately appear.
Nevertheless, it is possible that placing the memory device in a noisy environment may result in an errant WCBR signal being sent to the test vector decode circuit during a non-test mode. For example, memory devices are often subjected to a burn-in process, wherein the memory devices are operated at higher-than-usual voltages and temperatures in order to identify weak memory devices. This noisy process could result in random signals being transmitted through the write enable, CAS, and RAS paths so as to trigger a false WCBR signal and latch the test vector decode circuit. In that event, the test vector decode circuit would process the memory address inputs at their present random state. The resulting output vectors might not have the proper values. As a consequence, parts of the integrated device that should receive a particular value may no longer do so. For example, it is possible that one of the output vectors may represent an errant "ground V.sub.BB " signal transmitted at the wrong time. That would ground the substrate of the memory device, thereby causing a high current mode and eventual meltdown of the circuitry. Therefore, it would be a benefit to the art to be able to prevent the memory circuit from inadvertently entering a test mode.